A continuing trend in the semiconductor industry is increased densification and miniaturization of features. In fabricating semiconductor devices, including resistors, capacitors and transistors, device size must continue to shrink in order to increase the performance and lower the cost of ultra-large scale integrated (ULSI) circuits. Among the components that continue to reduce in scale are junctions, which are doped regions on a wafer where dopants such as boron, phosphorus and arsenic, are implanted into a silicon substrate. The dopants impart desired electrical properties to the wafer by allowing silicon, normally only a semiconducting material, to conduct current. Junctions are used to form source and drain (S/D) regions of MOS transistors. Devices now require shallow junctions, which are formed by implanting ions to shallow depths on the order of about 100-500 angstroms and typically about 300 angstroms or less. The formation of ultra-shallow junctions allows smaller device dimensions and higher circuit density.
Ion implantation is replacing diffusion as the standard technique for introducing conductivity-altering dopant materials into semiconductor wafers in most ULSI doping processes. FIG. 1 schematically illustrates a conventional ion beam implanter 10 for forming doped regions in a wafer 12. In a conventional beam-line type ion implantation system, a desired dopant material is ionized in an ion source 14 to form an ion beam 16, the ions are accelerated to a high velocity using an accelerator 18, and the ion beam 16 is directed at the wafer 12 situated on a wafer chuck 20. The depth to which ions are implanted in the wafer is obtained by controlling the energy of the ions as they impinge on the wafer surface. The beam current in implanters generally ranges between about 1 mA to 30 mA, depending on the implant species, energy and type of implanter. The ions penetrate the surface of the wafer and are embedded into the crystalline lattice of the semiconductor material. The number of implanted ions per unit area, or dose (φ), is related to beam current I (amperes), beam area A (cm2) and implant duration t (seconds), and typically ranges from 1011-1016 ions/cm2. The implanted substrate is subsequently annealed (e.g., at about 900-1,100° C.) in an inert gas (e.g., N2, etc.) to activate the dopants, i.e., transfer the dopants from impurities to carriers in the crystal lattice.
The reduction of device dimensions, for example, the shortened channel lengths of MOS transistors, creates a so-called short-channel effect (SCE). To minimize the short-channel effect, an ultra-shallow junction depth (xj) and low enough sheet resistance (Rs) are required for the source/drain (S/D) fabrication of MOS transistors. For example, for 45 nm technology node based on the International Technology Roadmap on Semiconductor 2005 (ITRS2005), it is required that the junction depth of S/D extension is shallower than 6.5 nm and the activated Rs of S/D extension is lower than 650 Ω/sq. To meet these requirements as device size shrinks, ultra-low energy (e.g., <1 keV for boron) ion implantation must be used.
Conventional beam-line ion implantation offers advantages over traditional diffusion techniques, including (1) precise control of dose and depth profile due to decoupling of the doping and annealing processes; (2) low temperature processing, which allows the use of photoresist as a mask; (3) the ability to use a wide selection of masking material (e.g., metal, polysilicon, photoresist, oxide, etc.); and (4) less sensitivity to surface cleaning procedures. However, despite the advantages of conventional beam-line ion implantation processes, there are several drawbacks relating to fundamental physical limitations such as space charge limits, intrinsic sputtering effects, and implant angle limits for non-planar structures for low energy implants. These limitations create problems in microelectronics manufacturing.
With conventional beam-line ion implantation processes, the ion beam and momentum of the ions impinging on the wafer causes sputtering of the silicon substrate during doping, resulting in the removal of doped silicon material. The sputtering effect by energetic ion bombardment during ion implantation both affects the structure of the devices and the as-implanted dopant profile. Etching, including sputtering and reactive ion etching (RIE), is known to cause retained dose saturation of the dopant and, in turn, sheet resistance (Rs) saturation in the wafer. The implant dose in the substrate is removed by etching so that the dose is saturated after the removed depth equals the implant range (Rp).
In FIG. 2, the retained boron dopant dose (atoms/cm2) and sheet resistance (Rs) (Ω/sq.) saturations is plotted as a function of nominal B implant dose (ions/cm2) by ultra-low energy (500 ev) boron (B) beam-line ion implants. As shown, the value of Rs does not fall below 650 Ω/sq. regardless of the duration (time period) of the ion implantation process (Shu Qin et al., “Measurement and analysis of deposition-etch characterization of BF3 plasma immersion ion implantation,” Review of Scientific Instruments 73(2): 840-842 (2002)). This demonstrates that for ultra-low energy implants, conventional beam-line ion implantation does not achieve the desired sheet resistance (Rs) due to its intrinsic sputtering effect.
It would be useful to provide a method for optimizing bean-line ion implants that overcomes these or other problems.